The so-called Fast Print or Killer Poke has much been talked about. It is a Commodore BASIC Poke command that is supposed to be able to destroy a PET computer. There have been claims that it is not possible to destroy a PET by this poke. Personally I never tried it on a possibly vulnerable PET and I know of no confirmed death. However, I know of a confirmed "Screen starts to behave funny so I switched it off". If you can confirm that a PET has been killed by such a poke (i.e. experienced it yourself, not just by word of mouth), please tell me!
Below I will go into the history, the technical details and why I think the poke might be able to kill a certain PET model. If you find any inaccuracy in the technical description, please let me know.
The very first PET models (board #1) had very slow video RAM. Its access rate was the same as the rate of the main memory, 1 MHz. Therefore only the CPU or the video logic could access the video RAM at any one cycle, but not both. To achieve proper operation, the CPU always has priority over the video circuitry. When the video logic wants to read byte of video data when the CPU accesses the video RAM, it reads invalid data. This results in "snow" on the screen.
To overcome the problem, Commdore did two things. First they used a special output line (CA2 of PIA1 at $E810 (59408)) that disabled the video output. It was also used as EOI output to the IEEE488 bus. On those PET models the screen blanked for a short period when the IEEE488 interface was used. Blanking the video with this line allowed to update the screen quickly, without provoking snow on the display. This feature was used by the kernal for scrolling, and by a few games to do some explosion effects. It has been removed in later models, and has nothing to do with the killer poke. In those later models this output only controls the IEEE488 EOI line. (According to Jim Butterfield's quote `"..screen snow and 'scroll-up flash' has been eliminated thanks to dynamic screen RAMs.." (quote from Jim Russo, The Transactor, May 1979)` it has been removed together with the introduction of the board#2 models. In those models the screen RAM is faster and allows 2 MHz access, video at Phi1 and CPU at Phi2.)
The second feature was the vertical retrace input at VIA Port B ($e840, 59456), bit 5. In the kernal's print routine there is a loop that waits for this input to become low. Thus the video memory is only used by the CPU in the off-screen area. Of course it takes a lot of time to wait for the vertical retrace when the electron beam is at the beginning of the screen. This is where the fast print poke comes in. The poke sets the VIA PB5 to low output. This way the kernal always thinks the electron beam is at the retrace (it always reads the output register value on port B for output pins, not the pin voltage level), and immediately prints to the screen. This is faster, but produces snow on the screen on the old PETs. The vertical retrace signal is generated by the video logic, that is discrete TTL in the old models (without the CRTC chip). It is also used as an interrupt input to generate the system interrupt (CB1, PIA1). When the board #3 was released the introduction of the CRTC video chip changed the situation radically. Here the CRTC produces the VSync signal, that is active only at a part of the retrace. Also it seems that this change made the PET vulnerable to the Poke. A possible explanation, however, is quite technical and given in the next section.
To understand the nature of the problem one has to know a bit about digital and analog electronics. First of all, we cannot assume that what we are talking about is purely digital in the sense that all voltages are 0V or 5V, and none else. Secondly we have to look at the databooks of the components involved, the 6522 and several TTL ICs. I will mention the necessary detail when needed.
What I will describe below has solely been analyzed from the schematics of the different PET models. Later I have confirmed the voltage drop with an oscilloscope on my CBM 8296. But I have no idea whether the analysis of the CRT electronics is correct after all. So please take it with a grain of salt.
The non-CRTC PET generate the retrace signal with the "master timing" electronics, where it was produced by a 74LS08 (C6 in the 2001 schematics on funet). This signal is also used in IC E9 (input to 74LS20) to blank the video signal on off-screen times. The signal itself, as I can see it, is not fed to the (analog) video (CRT i.e.) electronics. This means that the relevant input is a TTL input that recognizes everything above 2.4V as a logic 1.
In normal operation C6 produces the signal that is 5V for screen active and 0V for off-screen. The "speed" poke now is to set PB5 to a low output. However already in this case we have an unhealthy situation: The 74LS08 drives the line high and low according to the timing, but the VIA always pulls the line low. Obviously the 74LS08 wins, because otherwise the screen would be blank anyway (due to E9, 74LS20), but probably only because a TTL input recognizes even 2.4V only as a logic 1 (The datasheets - http://www.fairchildsemi.com/pf/DM/DM74LS08.html for example - say that the TTL output can source 0.4mA to pull a line high, and the VIA 6522 can drain 1.6mA. This would mean that the 6522 can always drain the line to a low voltage level. Why does the 74LS20 then read a logic 1, i.e. more than 2.4V? The solution is that the 74LS08 sources 0.4mA in normal operation, but it can source up to 20-100mA under short circuit conditions. A 6522 draining up to 1.6mA can surely count as some kind of short circuit condition. For normal operation (< 0.4mA) it is guaranteed that the output voltage is around 5V. For short circuit conditions the voltage is less. As the TTL input (74LS20) still reads the logic 1, we can conclude that the TTL output still sources enough current to keep the voltage above 2.4V. We have to assume that sourcing 4 times the nominal current will lower the voltage considerably from 5V, though. I would be grateful if someone could measure those voltages with an oscilloscope to confirm that theory.)
The timing for the Cathode Ray Tube is still done by the master timing electronics, i.e. VSync and HSync signals are not influenced by the poke.
When the video electronics was changed to use the CRTC chip, there was no more master timing electronics. So another way had to be found to generate the signal, esp. for the system interrupt. Therefore the CRTC VSync signal is used as a replacement signal. Again we have the same situation as above. One TTL output and a VIA 6522 driving the signal against each other. We will expect the same voltage drop as above.
This effect has in fact been observed - I have measured the VDRIVE pin of my 8296 with and without the poke. Without the poke I get a signal with an average voltage of about 4.7V to GND. With the poke, however, I get an average voltage of 1V to GND! The picture on my oscilloscope indeed shows that the voltage difference between the high level (display) and low level (retrace) with the poke reduces to about a fourth of the voltage without the poke!
In the CRTC PET the signal is not read by a TTL input, but is directly fed to analog the CRT electronics. The first input circuitry of the VSync signal seems to be the ramp generator.
The VDrive input of the early 8032 schematics (see http://www.funet.fi/pub/cbm/schematics/computers/pet/8032/321448.gif expects 5V for onscreen and 0V for flyback. As long as the Vdrive input is (much?) higher than 1.93V a current is simply integrated to get the ramp voltage (for the vertical beam position, see oscilloscope point (4)) A diode (D602) lets the TTL output draw the charge of C601 and the ramp generator goes to 0 when the VSync input goes to 0 (see oscillscope picture (3) & (4)) The DC voltage at (4) is around 1.93V (so the schematics says).
Now apply the poke to set Via PB to low output. If the ramp goes above the voltage of the TTL level (that might be lower than 5V because the VIA draws it) the flyback could be triggered earlier, because the diode drains C601 much earlier than it should. I don't say that the ramp is now steeper. I only say that the ramp might be stopped earlier. Probably some other effects also take place.
So in my opinion it could be possible that the observed voltage drop does weird things to the video circuitry. And feeding weird signals to a monitor can result in too high voltages generated by the flyback yokes, that could probably do quite some damage.
The effect did not happen on old PET, because the VIA was not connected to the VSync signal, but to the video signal generation, and thus restricted to the board itself.
Commodore seem to have been noticed of this behaviour and they changed the video electronics: Later (see http://www.funet.fi/pub/cbm/schematics/computers/pet/8032/8032034.gif) the analog electronics has been replaced by an integrated circuit, a TDA 1170. This could probably handle the reduced Vsync voltage.
In fact I even tried the poke on my 8296 with connected screen. As a late model I assumed it has the fix, but kept my finger close to the reset button, though. As far as I can see from the screen the CRT now simply does not get any sync anymore, the screen just moves.
PET index V1.0 (c) 1999 A. Fachat